CO |Gate-2006| Computer Organization 1. Consider two cache organizations: The first one is 32 KB 2-way set associative with 32-byte block size. The second one is of the same size but direct mapped. The size of an address is 32 bits in both cases. A 2-to-1 multiplexer has a latency of 0.6 ns while a …
CO |Gate-2007| Computer Organization Consider a 4-way set associative cache consisting of 128 lines with a line size of 64 words. The CPU generates a 20-bit address of a word in main memory. The number of bits in the TAG, LINE and WORD fields are respectively: [GATE – 2007] a. 9, 6, 5b. 7, 7, …
CO |Gate-2008| Computer Organization 1. For a magnetic disk with concentric circular tracks, the seek latency is not linearly proportional to the seek distance due to : [GATE – 2008] a. arm starting and stopping inertiab. non-uniform distribution of requestsc. higher capacity of tracks on the periphery of the platterd. use of unfair arm scheduling …
CO |Gate-2009| Computer Organization A CPU generally handles an interrupt by executing an interrupt service routine : [GATE – 2009] a. As soon as an interrupt is raised.b. By checking the interrupt register at the end of fetch cycle.c. By checking the interrupt register after finishing the execution of the current instruction.d. By checking the …
CO |Gate-2010| Computer Organization 1. A 5-stage pipelined processor has Instruction Fetch(IF),Instruction Decode(ID),Operand Fetch(OF),Perform Operation(PO)and Write Operand(WO)stages.The IF,ID,OF and WO stages take 1 clock cycle each for any instruction.The PO stage takes 1 clock cycle for ADD and SUB instructions,3 clock cycles for MUL instruction,and 6 clock cycles for DIV instruction respectively.Operand forwarding is used …
CO |Gate-2011| Computer Organization 1. Consider a hypothetical processor with an instruction of type LW R1, 20 (R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of constant 20 and the contents of register …
CO |Gate-2012| Computer Organization Register renaming is done in pipelined processors : [GATE – 2012] a. as an alternative to register allocation at compile timeb. for efficient access to function parameters and local variablesc. to handle certain kinds of hazardsd. as part of address translation Answer : c) A computer has a 256 KByte, 4-way …
CO |Gate-2013| Computer Organization 1. In a k-way set associative cache, the cache is divided into v sets, each of which consists of k lines. The lines of a set are placed in sequence one after another. The lines in set s are sequenced before the lines in set (s+1). The main memory blocks are …
CO |Gate-2014| Computer Organization A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers, each of which is 32 bits long. It needs to support 45 instructions, which have an immediate operand in addition to two register operands. Assuming that the immediate operand is an unsigned integer, the maximum value of …
CO |Gate-2015| Computer Organization 1. For computers based on three-address instruction formats, each address field can be used to specify which of the following: [GATE – 2015] (S1) A memory operand(S2) A processor register(S3) An implied accumulator register a. Either S1 or S2b. Either S2 or S3c. Only S2 and S3d. All of S1, S2 …