# DLD |Gate-2020| Previous Year Questions| Set-1

DLD |Gate-2020| Digital Logic Design

1. A multiplexer is placed between a group of 32 registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will move to the accumulator. The minimum number of select lines needed for the multiplexer is _____. [GATE – 2020]

a. 5
b. 6
c. 7
d. 8

2. If there are m input lines and n output lines for a decoder that is used to uniquely address a byte addressable 1 KB RAM, then the minimum value of m + n is ____. [GATE – 2020]

a. 1033
b. 1034
c. 1035
d. 1036

DLD |Gate-2020|

3. Consider the Boolean function z(a,b,c).

Which one of the following minterm lists represents the circuit given above? [GATE – 2020]

a. Z=Σ(0,1,3,7)
b. Z=Σ(2,4,5,6,7)
c. Z=Σ(1,4,5,6,7)
d. Z=Σ(2,3,5)

4. Consider three registers R1, R2 and R3 that store numbers in IEEE-754 single precision floating point format. Assume that R1 and R2 contain the values (in hexadecimal notation) 0x42200000 and 0xC1200000, respectively.
If R3 = R1/R2, what is the value stored in R3? [GATE – 2020]

a. 0x40800000
b. 0x83400000
c. 0xC8500000
d. 0xC0800000