# DLD |Gate-2019| Previous Year Questions| Set-2 DLD |Gate-2019| Digital Logic Design

1. In 16-bit 2’s complement representation, the decimal number -28 is: [GATE – 2019]

a. 1111 1111 1110 0100
b. 1111 1111 0001 1100
c. 0000 0000 1110 0100
d. 1000 0000 1110 0100

2. Two numbers are chosen independently and uniformly at random from the set {1, 2, …, 13}. The probability (rounded off to 3 decimal places) that their 4-bit (unsigned) binary representations have the same most significant bit is ______. [GATE – 2019]

a. 0.502
b. 0.461
c. 0.402
d. 0.561

3. Consider Z = X – Y, where X, Y and Z are all in sign-magnitude form. X and Y are each represented in n bits. To avoid overflow, the representation of Z would require a minimum of: [GATE – 2019]

a. n bits
b. n + 1 bits
c. n – 1 bits
d. n + 2 bits

DLD |Gate-2019|

4. Which one of the following is NOT a valid identity? [GATE – 2019]

a. (x + y) ⊕ z = x ⊕ (y + z)
b. (x ⊕ y) ⊕ z = x ⊕ (y ⊕ z)
c. x ⊕ y = x + y, if xy = 0
d. x ⊕ y = (xy + x’y’)’

5. What is the minimum number of 2-input NOR gates required to implement a 4-variable function function expressed in sum-of-minterms form as f = Σ(0, 2, 5, 7, 8, 10, 13, 15)? Assume that all the inputs and their complements are available. [GATE – 2019]

a. 1
b. 4
c. 2
d. 7
e. 3 (option not given)

6. Consider three 4-variable functions f1, f2 and f3, which are expressed in sum-of-minterms as

f1 = Σ(0, 2, 5, 8, 14),  f2 = Σ(2, 3, 6, 8, 14, 15),  f3 = Σ(2, 7, 11, 14)

For the following circuit with one AND gate and one XOR gate, the output function f can be expressed as: [GATE – 2019]

a. Σ (2, 14)
b. Σ (2, 7, 8, 11, 14)
c. Σ (7, 8, 11)
d. Σ (0, 2, 3, 5, 6, 7, 8, 11, 14, 15)