DLD |Gate-2017| Previous Year Questions| Set-4

Set-15 GATE-2006 DLD

DLD |Gate-2017| Digital Logic Design

1. The n-bit fixed-point representation of an unsigned real number X uses f bits for the fraction part. Let i = n-f. The range of decimal values for X in this representation is : [GATE – 2017]

a. 2-f to 2i
b. 2-f to (2i – 2-f)
c. 0 to 2i
d. 0 to (2i – 2-f )

Answer : d)

2. When two 8-bit numbers A7…A0 and B7…B0 in 2’s complement representation (with A0 and B0 as the least significant bits) are added using a ripple-carry adder, the sum bits obtained are S7…S0 and the carry bits are C7…C0. An overflow is said to have occurred if : [GATE – 2017]

a. the carry bit C7 is 1
b. all the carry bits (C7,…,C0) are 1



Answer : c)
DLD |Gate-2017|

3. Consider the Karnaugh map given below, where X represents “don’t care” and blank represents 0.

Assume for all inputs (a,b,c,d), the respective complements (a’,b’,c’,d’) are also available. The above logic is implemented using 2-input NOR gates only. The minimum number of gates required is _________. [GATE – 2017]

a. 1
b. 2
c. 3
d. 4

Answer : a)
DLD |Gate-2017|

4 . Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the input of the T flip-flop and the output of the T flip-flop is connected to the input of the D flip-flop. [GATE – 2017]

Initially, both Q0 and Q1 are set to 1 (before the 1st clock cycle). The outputs

a. Q1 Q0 after  the 3rd  cycle are 11 and after  the 4th cycle  are 00 respectively .
b. Q1 Q0 after  the 3rd  cycle are 11 and after  the 4th cycle  are 01 respectively .
c. Q1 Q0 after  the 3rd  cycle are 11 and after  the 4th cycle  are 11 respectively .
d. Q1 Q0 after  the 3rd  cycle are 11 and after  the 4th cycle  are 01 respectively .

Answer : b)

5. The representation of the value of a 16-bit unsigned integer X in hexadecimal number system is BCA9. The representation of the value of X in octal number system is : [GATE – 2017]

a. 136251
b. 736251
c. 571247
d .136252

Answer : a)

6. Given the following binary number in 32-bit (single precision) IEEE-754 format:


The decimal value closest to this floating-point number is : [GATE – 2017]

a. 1.45 × 101
b. 1.45 × 10
c. 2.27 × 10-1
d. 2.27 × 101

Answer : c)

6. Consider a quadratic equation x2 – 13x + 36 = 0 with coefficients in a base b. The solutions of this equation in the same base b are x = 5 and x = 6. Then b=________. [GATE – 2017]

a. 8
b. 9
c. 10
d. 11

Answer : a)

7. If w, x, y, z are Boolean variables, then which one of the following is INCORRECT? [GATE – 2017]

a. wx + w(x + y) + x(x + y) = x + wy
b. (w + y)(wxy + wyz) = wxy + wyz
c. (wx’ (y+z’))’ +w’x = w’ + x +y’z
d. (wx’(y+xz’) + w’x’)y = xy’

Answer : d)

8. Given f(w,x,y,z) = Σm(0,1,2,3,7,8,10) + Σd(5,6,11,15), where d represents the don’t-care condition in Karnaugh maps. Which of the following is a minimum product-of-sums (POS) form of f(w,x,y,z)? [GATE – 2017]

a. f = (w’ + z’)(x’ + z )
b. f = (w’ + z)(x + z)
c. f = (w + z)(x’ + z)
d. f = (w + z’)(x’ + z)

Answer : a)

9. Consider a binary code that consists of only four valid code words as given below:

00000, 01011, 10101, 11110

Let the minimum Hamming distance of the code be p and the maximum number of erroneous bits that can be corrected by the code be q. Then the values of p and q are : [GATE – 2017]

a. p=3 and q=1
b. p=3 and q=2
c. p=4 and q=1
d. p=4 and q=2

Answer : a)

OS – GATE Previous Year Questions
DS – GATE Previous Year Questions


Spread the love

Leave a Comment

Your email address will not be published. Required fields are marked *