# DLD |Gate-2016| Previous Year Questions| Set-5

DLD |Gate-2016| Digital Logic Design

1. Consider the Boolean operator with the following properties:

X#0 = x, x#1 = x’ , x#x = 0 and x#x’ = 1

Then x#y is equiavlent to : [GATE – 2016]

a. xy’ + x’y
b. xy’ + x’y’
c. ’y + xy
d. xy + x’y’

2. The 16-bit 2’s complement representation of an integer is 1111 1111 1111 0101; its decimal representation is __________. [GATE – 2016]

a. -11
b. -12
c. -13
d. -14

3. We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of J-K ﬂip-ﬂops required to implement this counter is __________. [GATE – 2016]

a. 3
b. 4
c. 5
d. 6

4. Consider the two cascaded 2-to-1 multiplexers as shown in the ﬁgure.

The minimal sum of products form of the output X is : [GATE – 2016]

a. P’Q’ + PQR
b. P’Q + QR
c. PQ +  P’Q’R
d. Q’R’ + PQR

5. Consider a carry lookahead adder for adding two n-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is __________. [GATE – 2016]

a. Θ(1)
b. Θ(log(n))
c. Θ(√n)
d. Θ(n)

DLD |Gate-2016|

6. Consider an eight-bit ripple-carry adder for computing the sum of A and B, where A and B are integers represented in 2’s complement form. If the decimal value of A is one, the decimal value of B that leads to the longest latency for the sum to stabilize is _________. [GATE – 2016]

a. -1
b. -2
c. -3
d. -4

7. Let, x1⊕x2⊕x3⊕x4 = 0 where x1, x2, x3, x4 are Boolean variables, and ⊕ is the XOR operator. Which one of the following must always be TRUE? [GATE – 2016]

a. x1x2x3x4 = 0
b. x1x2x3x4 = 0

c.

d. x1 + x2 + x3 + x4 = 0

8. Let X be the number of distinct 16-bit integers in 2’s complement representation. Let Y be the number of distinct 16-bit integers in sign magnitude representation.

Then X-Y is _________. [GATE – 2016]

a. 1
b. 2
c. 3
d. 4