DLD |Gate-2015| Previous Year Questions| Set-6

Set-15 GATE-2006 DLD

DLD |Gate-2015| Digital Logic Design

  1. Consider a 4-bit Johnson counter with an initial value of 0000. The counting sequence of this counter is : [GATE – 2015]

a. 0, 1, 3, 7, 15, 14, 12, 8, 0
b. 0, 1, 3, 5, 7, 9, 11, 13, 15, 0
c. 0, 2, 4, 6, 8, 10, 12, 14, 0
d. 0, 8, 12, 14, 15, 7, 3, 1, 0

Answer : d)


  1. The binary operator ≠ is defined by the following truth table 
pqp != q
000
011
101
110

Which one of the following is true about the binary operator ≠? [GATE – 2015]

a. Both commutative and associative
b. Commutative but not associative
c. Not commutative but associative
d. Neither commutative nor associative

Answer : a)


  1. A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flipflop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state-holding mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays. [GATE – 2015]

a. 0110110…
b. 0100100…
c. 011101110…
d. 011001100…

Answer : a)


  1. The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0,…….) is ___________. [GATE – 2015]

a. 2
b. 3
c. 4
d. 5

Answer : b)

  1. The number of min-terms after minimizing the following Boolean expression is ______  [D’ + AB’ + A’C + AC’D + A’C’D’]’ [GATE – 2015]

a. 1
b. 2
c. 3
d. 4

Answer : a)


  1. A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds. A 4-bit ripple-carry binary adder is implemented by using four full adders. The total propagation time of this 4-bit binary adder in microseconds is ____________. [GATE – 2015]

a. 19.1
b. 18.2
c. 19.2
d. 18.1

Answer : c)
DLD |Gate-2015|


  1. The total number of prime implicants of the function f(w,x,y,z) = Σ(0, 2, 4, 5, 6, 10) is ______. [GATE – 2015]

a. 1
b. 2
c. 4
d. 3

Answer : d)
DLD |Gate-2015|


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