# DLD |Gate-2010| Previous Year Questions| Set-11 DLD |Gate-2010| Digital Logic Design

1. The minterm expansion of  f(P,Q,R) = PQ + QR’ + PR’ is :  [GATE – 2010]

a. m2+m4+m6+m7
b. m0+m1+m3+m5
c. m0+m1+m6+m7
d. m2+m3+m4+m5

1. A main memory unit with a capacity of 4 megabytes is built using 1M 1-bit DRAM chips. Each DRAM chip has 1K rows of cells with 1K cells in each row. The time taken for a single refresh operation is 100 nanoseconds. The time required to perform one refresh operation on all the cells in the memory unit is : [GATE – 2010]

a. 100 nanoseconds
b. 100*210 nanoseconds
c. 100*220 nanoseconds
d. 3200*220 nanoseconds

1. P is a 16-bit signed integer. The 2’s complement representation of P is (F87B)16. The 2’s complement representation of 8*P is : [GATE – 2010]

a. (C3D8)16
b. (187B)16
c. (F878)16
d. (987B)16

1. The Boolean expression for the output ‘f’ of the multiplexer shown below is  : [GATE – 2010]

a. (P⊕Q⊕R)’
b. P+Q+R
c. P⊕Q⊕R
d. (P+Q+R )’

1. What is the Boolean expression for the output f of the combinational logic circuit of NOR gates given below? [GATE – 2010]

a. (Q + R)’
b. (P + Q)’
c. (P + R)’
d. (P + Q + R)’