DLD |Gate-2006| Digital Logic Design
- Consider numbers represented in 4-bit gray code. Let h3h2h1h0 be the gray code representation of a number n and let g3g2g1g0 be the gray code of (n+1) (modulo 16) value of the number. Which one of the following functions is correct? [GATE – 2006]
a. g0(h3h2h1h0) = Σ(1,2,3,6,10,13,14,15)
b. g1(h3h2h1h0) = Σ(4,9,10,11,12,13,14,15)
c. g2(h3h2h1h0) = Σ(2,4,5,6,7,12,13,15)
d. g3(h3h2h1h0) = Σ(0,1,6,7,10,11,12,13)
Answer : c)
- Consider a Boolean function f (w, x, y, z). Suppose that exactly one of its inputs is allowed to change at a time. If the function happens to be true for two input vectors i1 = 〈w1, x1, y1, z1〉 and i2 = 〈w2, x2, y2, z2〉, we would like the function to remain true as the input changes from vectors i1 to i2 (i1 and i2 differ in exactly one bit position), without becoming false momentarily. Let f(w, x, y, z) = ∑(5, 7, 11, 12, 13, 15). Which of the following cube covers of f will ensure that the required property is satisfied? [GATE – 2006]
a. w’xz, wxy’, xy’z, xyz, wyz
b. wxy, w’xz, wyz
c. wxy’z’, xz, wx’yz
d. wxy’, wyz, wxz, w’xz, xy’z, xyz
Answer : d)
- When multiplicand Y is multiplied by multiplier X = xn – 1xn-2 ….x0 using bit-pair recoding in Booth’s algorithm, partial products are generated according to the following table.
| Row | Xi+1 | Xi | xi-1 | Partial Product |
| 1 | 0 | 0 | 0 | 0 |
| 2 | 0 | 0 | 1 | Y |
| 3 | 0 | 1 | 0 | Y |
| 4 | 0 | 1 | 1 | 2Y |
| 5 | 1 | 0 | 0 | ? |
| 6 | 1 | 0 | 1 | -Y |
| 7 | 1 | 1 | 0 | -Y |
| 8 | 1 | 1 | 1 | ? |
The partial products for rows 5 and 8 are : [GATE – 2006]
a. 2Y and Y
b. -2Y and 2Y
c. -2Y and 0
d. 0 and Y
Answer : c)
- The majority function is a Boolean function f(x, y, z) that takes the value 1 whenever a majority of the variables x, y, z and 1. In the circuit diagram for the majority function shown below, the logic gates for the boxes labeled P and Q are, respectively, [GATE – 2006]
a. XOR, AND
b. XOR, XOR
c. OR, OR
d. OR, AND
Answer : d)
- The addition of 4-bit, two’s complement, binary numbers 1101 and 0100 results in : [GATE – 2006]
a. 0001 and an overflow
b. 1001 and no overflow
c. 0001 and no overflow
d. 1001 and an overflow
Answer : c)
- Consider the circuit in the diagram. The ⊕ operator represents Ex-OR. The D flipflops are initialized to zeroes (cleared).
The following data: 100110000 is supplied to the “data” terminal in nine clock cycles. After that the values of q2q1q0 are: [GATE – 2006]
a. 000
b. 001
c. 010
d. 101
Answer : c)
DLD |Gate-2006|