CO |Gate-2020| Computer Organization
1. Consider the following statements.
I. Daisy chaining is used to assign priorities in attending interrupts.
II. When a device raises a vectored interrupt, the CPU does polling to identify the source of the interrupt.
III. In polling, the CPU periodically checks the status bits to know if any device needs its attention.
IV. During DMA, both the CPU and DMA controller can be bus masters at the same time.
Which of the above statements is/are TRUE? [GATE – 2020]
a. I and IV only
b. I and III only
c. III only
d. I and II only
Answer : b)
2. A direct mapped cache memory of 1 MB has a block ize of 256 bytes. The cache has an access time of 3 ns and a hit rate of 94%. During a cache miss, it takes 20 ns to bring the first word of a block from the main memory, while each subsequent word takes 5 ns. The word size is 64 bits. The average memory access time in ns (round off to 1 decimal place) is _____. [GATE – 2020]
c. 13. 6
Answer : a)
3. Consider the following data path diagram.
Which one of the following is the correct order of execution of the above steps? [GATE – 2020]
a. 3, 5, 1, 2, 4
b. 1, 2, 4, 3, 5
c. 3, 5, 2, 1, 4
d. 2, 1, 4, 5, 3
Answer : c)
4. Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock cycles to complete an instruction. You are going to make a 5-stage pipeline out of this processor. Overheads associated with pipelining force you to operate the pipelined processor at 2 GHz. In a given program, assume that 30% are memory instructions, 60% are ALU instructions and the rest are branch instructions. 5% of the memory instructions cause stalls of 50 clock cycles each due to cache misses and 50% of the branch instructions cause stalls of 2 cycles each. Assume that there are no stalls associated with the execution of ALU instructions. For this program, the speedup achieved by the pipelined processor over the non-pipelined processor (round off to 2 decimal places) is _____. [GATE – 2020]
Answer : d)
5. A computer system with a word length of 32 bits has a 16 MB byte-addressable main memory and a 64 KB, 4-way set associative cache memory with a block size of 256 bytes. Consider the following four physical addresses represented in hexadecimal notation.
A1 = 0x42C8A4, A2 = 0x546888, A3 = 0x6A289C, A4 = 0x5E4880
Which one of the following is TRUE? [GATE – 2020]
a. A1 and A4 are mapped to different cache sets.
b. A2 and A3 are mapped to the same cache set.
c. A1 and A3 are mapped to the same cache set.
d. A3 and A4 are mapped to the same cache set.
Answer : b)
6. A processor has 64 registers and uses 16-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a 4-bit immediate value. Each R-type instruction contains an opcode and two register names. If there are 8 distinct I-type opcodes, then the maximum number of distinct R-type opcodes is _____. [GATE – 2020]
Answer : a)