CO |Gate-2019| Previous Year Questions| Set-2

Set-15 GATE-2006 CO

CO |Gate-2019| Computer Organization

1. The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by A15 to A0. What is the range of addresses (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal? [GATE – 2019]

a. C800 to C8FF
b. CA00 to CAFF
c. C800 to CFFF
d. DA00 to DFFF

Answer : c)

2. A certain processor uses a fully associative cache of size 16 kB. The cache block size is 16 bytes. Assume that the main memory is byte addressable and uses a 32-bit address. How many bits are required for the Tag and the Index fields resectively in the addresses generated by the processor? [GATE – 2019]

a. 28 bits and 0 bits
b. 24 bits and 0 bits
c. 28 bits and 4 bits
d. 24 bits and 4 bits

Answer : a)
CO |Gate-2019|

3. A certain processor deploys a single-level cache. The cache block size is 8 words and the word size is 4 bytes. The memory system uses a 60-MHz clock. To service a cache miss, the memory controller first takes 1 cycle to accept the starting address of the block, it then takes 3 cycles to fetch all the eight words of the block, and finally transmits the words of the requested block at the rate of 1 word per cycle. The maximum bandwidth for the memory system when the program running on the processor issues a series of read operations is ______ × 106 bytes/sec. [GATE – 2019]

a. 160
b. 145
c. 172
d. 124

Answer : a)


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