CO |Gate-2018| Previous Year Questions| Set-3

Set-15 GATE-2006 CO

CO |Gate-2018| Computer Organization

1. Consider the following processor design characteristics.

I. Register-to-register arithmetic operations only
II. Fixed-length instruction format
III. Hardwired control unit

Which of the characteristics above are used in the design of a RISC processor? [GATE – 2018]

a. I and II only
b. I, II and III
c. II and III only
d. I and III only

Answer : b)

2. A 32-bit wide main memory unit with a capacity of 1 GB is built using 256M×4-bit DRAM chips. The number of rows of memory cells in the DRAM chip is 214. The time taken to perform one refresh operation is 50 nanoseconds. The refresh period is 2 milliseconds. The percentage (rounded to the closest integer) of the time available for performing the memory read/write operations in the main memory unit is _________. [GATE – 2018]

a. 59%
b. 60%
c. 62%
d. 63%

Answer : a)
CO |Gate-2018|

3. The following are some events that occur after a device controller issues an interrupt while process L is under execution. [GATE – 2018]

(P) The processor pushes the process status of L onto the control stack.
(Q) The processor finishes the execution of the current instruction.
(R) The processor executes the interrupt service routine.
(S) The processor pops the process status of L from the control stack.
(T) The processor loads the new PC value based on the interrupt.


Answer : a)
CO |Gate-2018|

4. The size of the physical address space of a processor is 2P bytes. The word length is 2W bytes. The capacity of cache memory is 2N bytes. The size of each cache block is 2M words. For a K-way set-associative cache memory, the length (in number of bits) of the tag field is : [GATE – 2018]

a. P – N – log2K
b. P – N + log2K
c. P – N – M – W – log2K
d. P – N – M – W + log2K

Answer : b)

5. A processor has 16 integer registers (R0, R1, …, R15) and 64 floating point registers (F0, F1, …, F63). It uses a 2-byte instruction format. There are four categories of instructions: Type-1, Type-2, Type-3 and Type-4.Type-1 category consists of four instructions, each with 3 integer register operands (3Rs). Type-2 category consists of eight instructions, each with 2 floating point register operands (2Fs). Type-3 category consists of fourteen instructions, each with one integer register operand and one floating point register operand (1R+1F). Type-4 category consists of N instructions, each with a floating point register operand (1F).

The maximum value of N is ________. [GATE – 2018]

a. 32
b. 33
c. 34
d. 35

Answer : a)

6. The instruction pipeline of a RISC processor has the following stages: Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Writeback (WB). The IF, ID, OF and WB stages take 1 clock cycle each for every instruction. Consider a sequence of 100 instructions. In the PO stage, 40 instructions take 3 clock cycles each, 35 instructions take 2 clock cycles each, and the remaining 25 instructions take 1 clock cycle each. Assume that there are no data hazards and no control hazards.

The number of clock cycles required for completion of execution of the sequence of instructions is ___________. [GATE – 2018]

a. 219
b. 220
c. 221
d. 222

Answer : a)


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