CO |Gate-2016| Previous Year Questions| Set-5

Set-15 GATE-2006 CO

CO |Gate-2016| Computer Organization

  1. A processor can support a maximum memory of 4GB, where the memory is word-addressable (a word consists of two bytes). The size of the address bus of the processor is at least _________ bits. [GATE – 2016]

a. 31
b. 32
c. 33
d. 34

Answer : a)


  1. The size of the data count register of a DMA controller is 16 bits. The processor needs to transfer a file of 29,154 kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times the DMA controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is ________. [GATE – 2016]

a. 456
b. 457
c. 458
d. 459

Answer : a)


  1. The stage delays in a 4-stage pipeline are 800, 500, 400 and 300 picoseconds. The first stage (with delay 800 picoseconds) is replaced with a functionally equivalent design involving two stages with respective delays 600 and 350 picoseconds. The throughput increase of the pipeline is ________ percent. [GATE – 2016]

a. 33.34%
b. 33.36%
c. 33.33%
d. 33.35%

Answer : c)


  1. A processor has 40 distinct instructions and 24 general purpose registers. A 32-bit instruction word has an opcode, two register operands and an immediate operand. The number of bits available for the immediate operand field is __________. [GATE – 2016]

a. 19
b. 18
c. 17
d. 16

Answer : d)
CO |Gate-2016|


  1. Suppose the functions F and G can be computed in 5 and 3 nanoseconds by functional units UF and UG, respectively. Given two instances of UF and two instances of UG, it is required to implement the computation F(G(Xi)) for 1 ≤ i ≤ 10. Ignoring all other delays, the minimum time required to complete this computation is _________ nanoseconds. [GATE – 2016]

a. 31
b. 30
c. 28
d. 29

Answer : c)


  1. Consider a processor with 64 registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register r identifier, and a twelve-bit immediate value. Each instruction must be stored in memory in a byte-aligned fashion. If a program has 100 instructions, the amount of memory (in bytes) consumed by the program text is _________. [GATE – 2016]

a. 503
b. 500
c. 502
d. 502

Answer : b)


  1. The width of the physical address on a machine is 40 bits. The width of the tag field in a 512 KB 8-way set associative cache is _________ bits. [GATE – 2016]

a. 24
b. 25
c. 26
d. 27

Answer : a)
CO |Gate-2016|


  1. Consider a 3 GHz (gigahertz) processor with a three-stage pipeline and stage latencies τ1, τ2, τ3 and such that τ = 3τ2/4 = 2τ3. If the longest pipeline stage is split into two pipeline stages of equal latency, the new frequency is _________ GHz, ignoring delays in the pipeline registers. [GATE – 2016]

a. 4
b. 5
c. 6
d. 7

Answe : a)


  1. A file system uses an in-memory cache to cache disk blocks. The miss rate of the cache is shown in the figure. The latency to read a block from the cache is 1 ms and to read a block from the disk is 10 ms. Assume that the cost of checking whether a block exists in the cache is negligible. Available cache sizes are in multiples of 10 MB.

The smallest cache size required to ensure an average read latency of less than 6 ms is _______ MB. [GATE – 2016]

a. 33
b. 30
c. 32
d. 31

Answer : b)
CO |Gate-2016|


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