CO |Gate-2015| Previous Year Questions| Set-6

Set-15 GATE-2006 CO

CO |Gate-2015| Computer Organization

1. For computers based on three-address instruction formats, each address field can be used to specify which of the following: [GATE – 2015]

(S1) A memory operand
(S2) A processor register
(S3) An implied accumulator register

a. Either S1 or S2
b. Either S2 or S3
c. Only S2 and S3
d. All of S1, S2 and S3

Answer : a)


2. Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speed up achieved in this pipelined processor is __________. [GATE – 2015]

a. 3.2
b. 3.3
c. 3.4
d. 3.5

Answer : a)


3. Consider a disk pack with a seek time of 4 milliseconds and rotational speed of 10000 rotations per minute (RPM). It has 600 sectors per track and each sector can store 512 bytes of data. Consider a file stored in the disk. The file contains 2000 sectors. Assume that every sector access necessitates a seek, and the average rotational latency for accessing each sector is half of the time for one complete rotation. The total time (in milliseconds) needed to read the entire file is _________. [GATE – 2015]

a. 14024
b. 14023
c. 14022
d. 14020

Answer : d)


4. Assume that for a certain processor, a read request takes 50 nanoseconds on a cache miss and 5 nanoseconds on a cache hit. Suppose while running a program, it was observed that 80% of the processors read requests result in a cache hit. The average and access time in nanoseconds is  _______. [GATE – 2015]

a. 14
b. 15
c. 16
d. 17

Answer : a)


5. Consider a  processor with byte-addressable memory. Assume that all registers, including Program Counter (PC) and Program Status WOrd (PSW), are of size 2 byte. Astack in the main memory is impllemented from memory locatuons (0100)16 and it grows upward. The stack pointer (SP) points to the top element of the stack. The current value SP is (016E)16. The CALL instructions is of two words, the first word is the op-code and the second word is the starting address of the subroutine. (one word =2bytes). The CALL instructions is implemented as follows

  1. Store the current value of PC in the stack
  2. Store the values of PSW register in the stack
  3. Load the starting address of the subroutine in PC

The content of PC just before the fetch of a CALL instructions is (5FAo)16. After execution of the CALL instruction, the value of the stack pinter is : [GATE – 2015]

a. (016A)16
b. (016C)16
c. (0170)16
d. (0172)16

Answer : d)


6. Consider the sequence of machine instruction given below

MUL R5,R0,R1 DIV R6,R2,R3 ADD R7,R5,R6 SUB R8,R7,R4 In the above sequence, R0 to R8 are general purpose registraters. In the instructions shown, the first register stores the result of the operation performed on the second and the third registers. This sequence of instructions is to be executed in a pipelined instruction processor with the following 4 stages: (1) Instruction Fetch and Decode (IF), (2) Operand Fetch (OF), (3) Perfom Operations (PO) and (4) Write back the result (WB). The IF, OF and WB stages take 1 clock cycle each instruction The PO stahe takes 1 clock cycle for ADD or SUB instruction, 3 clock cycles for MUL instruction and 5 clock cycles for DIV instructions. The pipelined processor uses operand foewarding from the PO stage to the OF stage. The number of clock cycles taken for the execution of the aboce sequence of instructions is _______ [GATE – 2015]

a. 11
b. 12
c. 13
d. 14

Answer  : c)
CO |Gate-2015|


7. Consider the following reservation table for a pipeline having three stages S1, S2 and S3.

     Time –>
—————————–
      1    2   3    4     5
—————————–
S1  | X  |   |   |    |  X |   
S2  |    | X |   | X  |    |
S3  |    |   | X |    |    |

The minimum average latency (MAL) is __________      [GATE – 2015]

a. 4
b. 5
c. 6
d. 7

Answer : a)
CO |Gate-2015|


8. Consider the following code sequence having five instruction |1 to 15. Each of these instructions has the following format  : [GATE – 2015]

OP Ri, Rj, Rk

Where operations OP is performed on contents of registers Rj and Rk and the result is stored in register Ri.

I1 : ADD R1, R2, R3
   I2 : MUL R7, R1, R3
   I3 : SUB R4, R1, R5
   I4 : ADD R3, R2, R4
I5 : MUL R7, R8, R9

Consider the following three statements:

S1: There is an anti-dependence between instructions I2 and I5.
S2: There is an anti-dependence between instructions I2 and I4.
S3: Within an instruction pipeline an anti-dependence always

creates one or more stalls.

a. Only S1 is true
b. Only S2 is true
c. Only S1 and S3 are true
d. Only S2 and S3 are true

Answer : b)
CO |Gate-2015|


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