CO |Gate-2014| Previous Year Questions| Set-7

Set-15 GATE-2006 CO

CO |Gate-2014| Computer Organization

  1. A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers, each of which is 32 bits long.  It needs to support 45 instructions, which have an immediate operand in addition to two register operands.  Assuming that the immediate operand is an unsigned integer, the maximum value of the immediate operand is ____________.  [GATE – 2014]

a. 16383
b. 16384
c. 16385
d. 16386

Answer : a)


  1. Consider two processors P1 and P2 executing the same instruction set. Assume that under identical conditions, for the same input, a program running on P2 takes 25% less time but incurs 20% more CPI (clock cycles per instruction) as compared to the program running on P1. If the clock frequency of P1 is 1GHz, then the clock frequency of P2 (in GHz) is _________.  [GATE – 2014]

a. 1.9
b. 1.8
c. 1.7
d. 1.6

Answer : d)


  1. A 4-way set-associative cache memory unit with a capacity of 16 KB is built using a block size of 8 words. The word length is 32 bits. The size of the physical address space is 4 GB. The number of bits for the TAG field is __________.  [GATE – 2014]

a. 21
b. 20
c. 22
d. 23

Answer : b)


  1. Suppose a stack implementation supports an instruction REVERSE, which reverses the order of elements on the stack, in addition to the PUSH and POP instructions. Which one of the following statements is TRUE with respect to this modified stack? [GATE – 2014]

a. A queue cannot be implemented using this stack.
b. A queue can be implemented where ENQUEUE takes a single instruction and DEQUEUE takes a sequence of two instructions.
c. A queue can be implemented where ENQUEUE takes a sequence of three instructions and DEQUEUE takes a single instruction.
d. A queue can be implemented where both ENQUEUE and DEQUEUE take a single instruction each.

Answer : c)


  1. In designing a computer’s cache system, the cache block (or cache line) size is an important parameter.  Which one of the following statements is correct in this context? [GATE – 2014]

a. A smaller block size implies better spatial locality
b. A smaller block size implies a smaller cache tag and hence lower cache tag overhead
c. A smaller block size implies a larger cache tag and hence lower cache hit time
d. A smaller block size incurs a lower cache miss penalty

Answer : d)


  1. If the associativity of a processor cache is doubled while keeping the capacity and block size unchanged, which one of the following is guaranteed to be NOT affected? [GATE – 2014]

a. Width of processor to main memory data bus
b. Width of way selection multiplexor
c. Width of set index decoder
d. Width of tag comparator

Answer : a)


  1. The value of a float type variable is represented using the single-precision 32-bit floating point format of IEEE-754 standard that uses 1 bit for sign, 8 bits for biased exponent and 23 bits for mantissa. A float type variable X is assigned the decimal value of −14.25. The representation of X in hexadecimal notation is : [GATE – 2014]

a. C1640000H
b. 416C0000H
c. 41640000H
d. C16C0000H

Answer : a)


  1. Consider a main memory system that consists of 8 memory modules attached to the system bus, which is one word wide. When a write request is made, the bus is occupied for 100 nanoseconds (ns) by the data, address, and control signals. During the same 100 ns, and for 500 ns thereafter, the addressed memory module executes one cycle accepting and storing the data. The (internal) operation of different memory modules may overlap in time, but only one request can be on the bus at any time. The maximum number of stores (of one word each) that can be initiated in 1 millisecond is ____________  [GATE – 2014]

a. 10001
b. 10000
c. 10002
d. 10003

Answer : b)
CO |Gate-2014|


  1. Consider the following processors (ns stands for nanoseconds). Assume that the pipeline registers have zero latency. P1: Four-stage pipeline with stage latencies 1 ns, 2 ns, 2 ns, 1 ns. P2: Four-stage pipeline with stage latencies 1 ns, 1.5 ns, 1.5 ns, 1.5 ns. P3: Five-stage pipeline with stage latencies 0.5 ns, 1 ns, 1 ns, 0.6 ns, 1 ns. P4: Five-stage pipeline with stage latencies 0.5 ns, 0.5 ns, 1 ns, 1 ns, 1.1 ns. Which processor has the highest peak clock frequency? [GATE – 2014]

a. P1
b. P2
c. P3
d. P4

Answer : c)
CO |Gate-2014|


  1. An instruction pipeline has five stages, namely, instruction fetch (IF), instruction decode and register fetch (ID/RF), instruction execution (EX), memory access (MEM), and register writeback (WB) with stage latencies 1 ns, 2.2 ns, 2 ns, 1 ns, and 0.75 ns, respectively (ns stands for nanoseconds). To gain in terms of frequency, the designers have decided to split the ID/RF stage into three stages (ID, RF1, RF2) each of latency 2.2/3 ns. Also, the EX stage is split into two stages (EX1, EX2) each of latency 1 ns. The new design has a total of eight pipeline stages. A program has 20% branch instructions which execute in the EX stage and produce the next instruction pointer at the end of the EX stage in the old design and at the end of the EX2 stage in the new design. The IF stage stalls after fetching a branch instruction until the next instruction pointer is computed. All instructions other than the branch instruction have an average CPI of one in both the designs. The execution times of this program on the old and the new design are P and Q nanoseconds, respectively. The value of P/Q is __________. [GATE – 2014]

a. 1.54
b. 1.55
c. 1.56
d. 1.57

Answer : a)
CO |Gate-2014|


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