CO |Gate-2013| Previous Year Questions| Set-8

Set-15 GATE-2006 CO

CO |Gate-2013| Computer Organization

1. In a k-way set associative cache, the cache is divided into v sets, each of which consists of k lines. The lines of a set are placed in sequence one after another. The lines in set s are sequenced before the lines in set (s+1). The main memory blocks are numbered 0 onwards. The main memory block numbered j must be mapped to any one of the cache lines from : [GATE – 2013]

a. (j mod v) * k to (j mod v) * k + (k-1)
b. (j mod v) to (j mod v) + (k-1)
c. (j mod k) to (j mod k) + (v-1)
d. (j mod k) * v to (j mod k) * v + (v-1)

Answer : a)

2. Consider the following sequence of micro-operations.

     MBR ← PC
     MAR ← X 
     PC ← Y 
     Memory ← MBR

Which one of the following is a possible operation performed by this sequence? [GATE – 2013]

a. Instruction fetch
b. Operand fetch
c. Conditional branch
d. Initiation of interrupt service

Answer : d)

3. Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 12 instructions I1, I2, I3, …, I12 is executed in this pipelined processor. Instruction I4 is the only branch instruction and its branch target is I9. If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is : [GATE – 2013]

a. 132
b. 165
c. 176
d. 328

Answer :  b)

4. A RAM chip has a capacity of 1024 words of 8 bits each (1K×8). The number of 2×4 decoders with enable line needed to construct a 16K×16 RAM from 1K×8 RAM is : [GATE – 2013]

a. 4
b. 6
c. 5
d. 7

Answer : c)

5. The following code segment is executed on a processor which allows only register operands in its instructions. Each instruction can have atmost two source operands and one destination operand. Assume that all variables are dead after this code segment.

   c = a + b;
   d = c * a;
   e = c + a;
   x = c * c;
   if (x > a) {
      y = a * a;
   else {
     d = d * d;
     e = e * e;

Suppose the instruction set architecture of the processor has only two registers. The only allowed compiler optimization is code motion, which moves statements from one place to another while preserving correctness. What is the minimum number of spills to memory in the compiled code? [GATE – 2013]

a. 3
b. 4
c. 5
d. 6

Answer : b)
CO |Gate-2013|


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