CO |Gate-2011| Previous Year Questions| Set-10

Set-15 GATE-2006 CO

CO |Gate-2011| Computer Organization

1. Consider a hypothetical processor with an instruction of type LW R1, 20 (R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of constant 20 and the contents of register R2. Which of the following best reflects the addressing mode implemented by this instruction for the operand memory? [GATE – 2011]

a. Immediate Addressing
b. Register Addressing
c. Register Indirect Scaled Addressing
d. Base Indexed Addressing

Answer : d)

2. A computer handles several interrupt sources of which the following are relevant for this question. [GATE – 2011]

. Interrupt from CPU temperature sensor (raises interrupt if
  CPU temperature is too high)
. Interrupt from Mouse(raises interrupt if the mouse is moved
  or a button is pressed)
. Interrupt from Keyboard(raises interrupt when a key is
  pressed or released)
. Interrupt from Hard Disk(raises interrupt when a disk
  read is completed)

Which one of these will be handled at the HIGHEST priority?

a. Interrupt from Hard Dist
b. Interrupt from CPU temperature sensor
c. Interrupt from Keyboard
d. Interrupt from Mouse

Answer : b)

3. Consider an instruction pipeline with four stages (S1, S2, S3 and S4) each with combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline registers are as given in the figure:

What is the approximate speed up of the pipeline in steady state under ideal conditions when compared to the corresponding non-pipeline implementation?     [GATE – 2011]

a. 4.0
b. 1.1
c. 2.5
d. 3.0

Answer : c)

4. An 8KB direct-mapped write-back cache is organized as multiple blocks, each of size 32-bytes. The processor generates 32-bit addresses. The cache controller maintains the tag information for each cache block comprising of the following. 1 Valid bit 1 Modified bit As many bits as the minimum needed to identify the memory block mapped in the cache. What is the total size of memory needed at the cache controller to store meta-data (tags) for the cache? [GATE – 2011]

a. 4864 bits
b. 6144 bits
c. 6656 bits
d. 5376 bits

Answer : d)

5. An application loads 100 libraries at startup. Loading each library requires exactly one disk access. The seek time of the disk to a random location is given as 10 ms. Rotational speed of disk is 6000 rpm. If all 100 libraries are loaded from random locations on the disk, how long does it take to load all libraries? (The time to transfer data from the disk block once the head has been positioned at the start of the block may be neglected). [GATE – 2011]

a. 0.50 s
b. 1.50 s
c. 1.25 s
d. 1.00 s

Answer : b)
CO |Gate-2011|

6. On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory.

Initialize the address register
              Initialize the count to 500
        LOOP: Load a byte from device
              Store in memory at address given by address register
              Increment the address register
              Decrement the count
             If count != 0 go to LOOP

Assume that each statement in this program is equivalent to machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute. The designer of the system also has an alternate approach of using DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory. What is the approximate speedup when the DMA controller based design is used in place of the interrupt driven program based input-output? [GATE – 2011]

a. 3.4
b. 4.4
c. 5.1
d. 6.7

Answer : a)
CO |Gate-2011|


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