CO |Gate-2008| Previous Year Questions| Set-13

Set-15 GATE-2006 CO

CO |Gate-2008| Computer Organization

1. For a magnetic disk with concentric circular tracks, the seek latency is not linearly proportional to the seek distance due to : [GATE – 2008]

a. arm starting and stopping inertia
b. non-uniform distribution of requests
c. higher capacity of tracks on the periphery of the platter
d. use of unfair arm scheduling policies

Answer : a)


2. Which of the following is/are true of the auto-increment addressing mode? I.It is useful in creating self-relocating code II.If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation III.The amount of increment depends on the size of the data item accessed : [GATE – 2008]

a. I only
b. II only
c. III only
d. II and III only

Answer : c)


3. Which of the following must be true for the RFE (Return From Exception) instruction on a general purpose processor? I.It must be a trap instruction II.It must be a privileged instruction III.An exception cannot be allowed to occur during execution of an RFE instruction : [GATE – 2008]

a. I only
b. II only
c. I and II only
d. I, II and III only

Answer : d)


4. For inclusion to hold between two cache levels L1 and L2 in a multi-level cache hierarchy, which of the following are necessary? I.L1 must be a write-through cache II.L2 must be a write-through cache III.The associativity of L2 must be greater than that of L1 IV.The L2 cache must be at least as large as the L1 cache  : [GATE – 2008]

a. IV only
b. I and IV only
c. I, III and IV only
d. I, II, III and IV

Answer : a)


5. Which of the following are NOT true in a pipelined processor? I.Bypassing can handle all RAW hazards II.Register renaming can eliminate all register carried WAR hazards III.Control hazard penalties can be eliminated by dynamic branch prediction  : [GATE – 2008] 

a. I and II only
b. I and III only
c. II and III only
d. I, II and III

Answer : b)


6. The use of multiple register windows with overlap causes a reduction in the number of memory accesses for I.Function locals and parameters II.Register saves and restores III.Instruction fetches : [GATE – 2008]

a. I only
b. II only
c. III only
d. I, II and III

Answer : a)


7. In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is : [GATE – 2008]

a. Before effective address calculation has started
b. During effective address calculation
c. After effective address calculation has completed
d. After data cache lookup has completed

Answer : c)


8. Consider a machine with a 2-way set associative data cache of size 64Kbytes and block size 16bytes. The cache is managed using 32 bit virtual addresses and the page size is 4Kbyts. A program to be run on this machine begins as follows: double ARR [1024][1024]; int       i,          j         ; /* Initialize array ARR to 0.0 * / for (i = 0;i < 1024; i + +) for (j = 0; j < 1024; j + +) ARR [i]   [j] = 0.0; The size of double is 8Bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored in row major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by the program are those to array ARR The total size of the tags in the cache directory is : [GATE – 2008]

a. 32 Kbits
b. 34 Kbits
c. 64 Kbits
d. 68 Kbits

Answer  : d)


9. Consider a machine with a 2-way set associative data cache of size 64Kbytes and block size 16bytes. The cache is managed using 32 bit virtual addresses and the page size is 4Kbyts. A program to be run on this machine begins as follows:   double ARR [1024][1024]; int       i,          j         ; /* Initialize array ARR to 0.0 * / for (i = 0;i < 1024; i + +) for (j = 0; j < 1024; j + +) ARR [i]   [j] = 0.0; The size of double is 8Bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored in row major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by the program are those to array ARR Which of the following array elements has the same cache index as ARR [0] [0]? [GATE – 2008]

a. ARR [0] [4]
b. ARR [4] [0]
c. ARR [0] [5]
d. ARR [5] [0]

Answer : b)


10. Consider a machine with a 2-way set associative data cache of size 64Kbytes and block size 16bytes. The cache is managed using 32 bit virtual addresses and the page size is 4Kbyts. A program to be run on this machine begins as follows:   double ARR [1024][1024]; int       i,          j         ; /* Initialize array ARR to 0.0 * / for (i = 0;i < 1024; i + +) for (j = 0; j < 1024; j + +) ARR [i]   [j] = 0.0; The size of double is 8Bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored in row major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by the program are those to array ARR The cache hit ratio for this initialization loop is :  [GATE – 2008]

a. 0 %
b. 25%
c. 50%
d. 75%

Answer : c)


11. Delayed branching can help in the handling of control hazards For all delayed conditional branch instructions, irrespective of whether the condition evaluates to true or false : [GATE – 2008]

a. The instruction following the conditional branch instruction in memory is executed.
b. The first instruction in the fall through path is executed.
c. The first instruction in the taken path is executed.
d. The branch takes longer to execute than any other instruction.

Answer : a)


12. Delayed branching can help in the handling of control hazards The following code is to run on a pipelined processor with one branch delay slot: I1 : ADD R2 ¬ R7 + R8 I2 :    SUB  R4 ¬ R5 – R6 I3 :    ADD R1 ¬ R2 + R3 I4 :    STORE Memory [R4] ¬ R1 BRANCH to Label if R1 = = 0 Which of the instructions I1, I2, I3 or I4 can legitimately occupy the delay slot without any other program modification?  [GATE – 2008]

a. I1
b. I2
c. I3
d. I4

Answer : d)


13. How many bytes of data can be sent in 15 seconds over a serial link with baud rate of 9600 in asynchronous mode with odd parity and two stop bits in the frame? [GATE – 2008]

a. 10,000 bytes
b. 12,000 bytes
c. 15,000 bytes
d. 27,000 bytes

Answer : b)


14. Assume that EA = (X)+ is the effective address equal to the contents of location X, with X incremented by one word length after the effective address is calculated; EA = −(X) is the effective address equal to the contents of location X, with X decremented by one word length before the effective address is calculated; EA = (X)− is the effective address equal to the contents of location X, with X decremented by one word length after the effective address is calculated. The format of the instruction is (opcode, source, destination), which means (destination ← source op destination). Using X as a stack pointer, which of the following instructions can pop the top two elements from the stack, perform the addition operation and push the result back to the stack. [GATE – 2008]

a. ADD (X)−, (X)
b. ADD (X), (X)−
c. ADD −(X), (X)+
d. ADD −(X), (X)+

Answer : a)


15. Consider a CPU where all the instructions require 7 clock cycles to complete execution. There are 140 instructions in the instruction set. It is found that 125 control signals are needed to be generated by the control unit. While designing the horizontal microprogrammed control unit, single address field format is used for branch control logic. What is the minimum size of the control word and control address register? [GATE – 2008]

a. 125, 7
b. 125, 10
c. 135, 7
d. 135, 10

Answer : d)
CO |Gate-2008|


16. A non pipelined single cycle processor operating at 100 MHz is converted into a synchro­nous pipelined processor with five stages requiring 2.5 nsec, 1.5 nsec, 2 nsec, 1.5 nsec and 2.5 nsec, respectively. The delay of the latches is 0.5 nsec. The speedup of the pipeline processor for a large number of instructions is : [GATE – 2008]

a. 4.5
b. 4.0
c. 3.33
d. 3.0

Answer :  c)
CO |Gate-2008|


17. Consider a computer with a 4-ways set-associative mapped cache of the following characteristics: a total of 1 MB of main memory, a word size of 1 byte, a block size of 128 words and a cache size of 8 KB. The number of bits in the TAG, SET and WORD fields, respectively are: [GATE – 2008]

a. 7, 6, 7
b.8, 5, 7
c. 8, 6, 6
d. 9, 4, 7

Answer : d)
CO |Gate-2008|


18. Consider a computer with a 4-ways set-associative mapped cache of the following character­istics: a total of 1 MB of main memory, a word size of 1 byte, a block size of 128 words and a cache size of 8 KB. While accessing the memory location 0C795H by the CPU, the contents of the TAG field of the corresponding cache line is : [GATE – 2008]

a. 000011000
b. 110001111
c. 00011000
d. 110010101

Answer : a)
CO |Gate-2008|


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