CO |Gate-2006| Previous Year Questions| Set-15

Set-15 GATE-2006 CO

CO |Gate-2006| Computer Organization

1. Consider two cache organizations: The first one is 32 KB 2-way set associative with 32-byte block size. The second one is of the same size but direct mapped. The size of an address is 32 bits in both cases. A 2-to-1 multiplexer has a latency of 0.6 ns while a kbit comparator has a latency of k/10 ns. The hit latency of the set associative organization is h1 while that of the direct mapped one is h2. The value of h1 is: [GATE – 2006]

a. 2.4 ns
b. 2.3 ns
c. 1.8 ns
d. 1.7 ns

Answer : a)


2. A CPU has 24-bit instructions. A program starts at address 300 (in decimal). Which one of the following is a legal program counter (all values in decimal)? [GATE – 2006]

a. 400
b. 500
c. 600
d. 700

Answer : c)


3. A CPU has a 32 KB direct mapped cache with 128-byte block size. Suppose A is a twodimensional array of size 512×512 with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2. P1:

for (i=0; i<512; i++)
{   
 for (j=0; j<512; j++)
{      
 x += A[i][j];   
 }
}

P2:

for (i=0; i<512; i++)
{    
for (j=0; j<512; j++)
{       
x += A[j][i];    
}
}

P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are in registers. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2 . The value of the ratio M1/M2 is: [GATE – 2006]

a. 0
b. 1/16
c. 1/8
d. 16

Answer : b)


4. A CPU has a 32 KB direct mapped cache with 128-byte block size. Suppose A is a twodimensional array of size 512×512 with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2. P1:

for (i=0; i<512; i++)
{   
 for (j=0; j<512; j++)
{    
x += A[i][j];  
  }
}

P2:

for (i=0; i<512; i++)
{   
 for (j=0; j<512; j++)
{    
   x += A[j][i];
   }
}

P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are in registers. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2 . The value of M1 is: [GATE – 2006]

a. 0
b. 2048
c. 16384
d. 262144

Answer : c)


5. Consider a new instruction named branch-on-bit-set (mnemonic bbs). The instruction “bbs reg, pos, label” jumps to label if bit in position pos of register operand reg is one. A register is 32 bits wide and the bits are numbered 0 to 31, bit in position 0 being the least significant. Consider the following emulation of this instruction on a processor that does not have bbs implemented. temp¬reg & mask Branch to label if temp is non-zero. The variable temp is a temporary register. For correct emulation, the variable mask must be generated by:  [GATE – 2006]

a. mask ← 0×1 ←pos
b. mask ← 0×ffffffff ← pos
c. mask ← pos
d. mask ← 0×f

Answer : a)


6. A CPU has a five-stage pipeline and runs at 1 GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the target address and evaluates the condition in the third stage of the pipeline. The processor stops fetching new instructions following a conditional branch until the branch outcome is known. A program executes 109 instructions out of which 20% are conditional branches. If each instruction takes one cycle to complete on average, the total execution time of the program is: [GATE – 2006]

a. 92 ns
b. 104 ns
c. 172 ns
d. 184 ns

Answer : d)


7. A CPU has a five-stage pipeline and runs at 1 GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the target address and evaluates the condition in the third stage of the pipeline. The processor stops fetching new instructions following a conditional branch until the branch outcome is known. A program executes 109 instructions out of which 20% are conditional branches. If each instruction takes one cycle to complete on average, the total execution time of the program is: [GATE – 2006]

a. 1.0 second
b. 1.2 second
c. 1.4 second
d. 1.6 second

Answer : c)


8. Which of the following DMA transfer modes and interrupt handling mechanisms will enable the highest I/O band-width? [GATE – 2006]

a. Transparent DMA and Polling interrupts
b. Cycle-stealing and Vectored interrupts
c. Block transfer and Vectored interrupts
d. Block transfer and Polling interrupts

Answer : c)


9. Which of the following statements about relative addressing mode is FALSE? [GATE – 2006]

a. It enables reduced instruction size
b. It enables easy relocation of data
c. It allows indexing of array elements with same instruction
d. It enables faster address calculations than absolute addressing

Answer : d)
CO |Gate-2006|


10. The memory locations 1000, 1001 and 1020 have data values 18, 1 and 16 respectively before the following program is executed. MOVI Rs, 1 ; Move immediate LOAD Rd, 1000(Rs) ; Load from memory ADDI Rd, 1000 ; Add immediate STOREI 0(Rd), 20 ; Store immediate Which of the statements below is TRUE after the program is executed ? [GATE – 2006]

a. Memory location 1001 has value 20
b. Memory location 1021 has value 20
c. Memory location 1020 has value 20
d. Memory location 1000 has value 20

Answer : a)
CO |Gate-2006|


11. A cache line is 64 bytes. The main memory has latency 32 ns and bandwidth 1 GBytes/s. The time required to fetch the entire cache line from the main memory is : [GATE – 2006]

a. 32 ns
b. 64 ns
c. 96 ns
d. 128 ns

Answer : c)
CO |Gate-2006|


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