DLD |Gate-2006| Digital Logic Design Consider numbers represented in 4-bit gray code. Let h3h2h1h0 be the gray code representation of a number n and let g3g2g1g0 be the gray code of (n+1) (modulo 16) value of the number. Which one of the following functions is correct? [GATE – 2006] a. g0(h3h2h1h0) = Σ(1,2,3,6,10,13,14,15)b. g1(h3h2h1h0) = Σ(4,9,10,11,12,13,14,15)c. g2(h3h2h1h0) = Σ(2,4,5,6,7,12,13,15)d. g3(h3h2h1h0) …
DLD |Gate-2007| Digital Logic Design What is the maximum number of different Boolean functions involving n Boolean variables? [GATE – 2007] a. n2b. 2nc. 22nd. 2n2 Answer : c) How many 3-to-8 line decoders with an enable input are needed to construct a 6-to-64 line decoder without using any other logic gates? [GATE – 2007] …
DLD |Gate-2008| Digital Logic Design In the IEEE floating point representation, the hexadecimal value 0×00000000 corresponds to : [GATE – 2008] a. the normalized value 2-127b. the normalized value 2-126c. the normalized value +0d. the special value +0 Answer : d) Let r denote number system radix. The only value(s) of r that satisfy the …
DLD |Gate-2009| Digital Logic Design (1217)8 is equivalent to : [GATE – 2009] a. (1217)16b. (028F)16c. (2297)10d. (0B17)16 Answer : b) What is the minimum number of gates required to implement the Boolean function (AB+C) if we have to use only 2-input NOR gates? [GATE – 2009] a. 2b. 3c. 4d. 5 Answer : b) How many 32K × …
DLD |Gate-2010| Digital Logic Design The minterm expansion of f(P,Q,R) = PQ + QR’ + PR’ is : [GATE – 2010] a. m2+m4+m6+m7b. m0+m1+m3+m5c. m0+m1+m6+m7d. m2+m3+m4+m5 Answer : a) A main memory unit with a capacity of 4 megabytes is built using 1M 1-bit DRAM chips. Each DRAM chip has 1K rows of cells with …
DLD |Gate-2011| Digital Logic Design 1. The simplified SOP (sum of product) form of the boolean expression (P + Q’ + R’).(P + Q’ + R). (P + Q + R’) : [GATE – 2011] a. (P’Q + R’)b. (PQ’ + R’)c. (P’Q + R)d. P + Q’R’ Answer : d) 2. The minimum number …
DLD |Gate-2012| Digital Logic Design The truth table X Y f(X,Y) 0 0 0 0 1 0 1 0 1 1 1 1 represents the Boolean function : [GATE – 2012] a. Xb. X + Yc. X ⊕ Yd. Y Answer : a) The decimal value 0.5 in IEEE single precision floating point representation has …
DLD |Gate-2013| Digital Logic Design The smallest integer that can be represented by an 8-bit number in 2’s complement form is : [GATE – 2013] a. -256b. -128c. -127d. 0 Answer : b) In the following truth table, V = 1 if and only if the input is valid. What function does the truth table …
DLD |Gate-2014| Digital Logic Design 1. Consider the following Boolean expression for F: F(P, Q, R, S) = PQ + P’QR + P’QR’S The minimal sum-of-products form of F is : [GATE – 2014] a. PQ + QR + QSb. P + Q + R + Sc. P’ + Q’ + R’ + S’d. P’R …
DLD |Gate-2015| Digital Logic Design Consider a 4-bit Johnson counter with an initial value of 0000. The counting sequence of this counter is : [GATE – 2015] a. 0, 1, 3, 7, 15, 14, 12, 8, 0b. 0, 1, 3, 5, 7, 9, 11, 13, 15, 0c. 0, 2, 4, 6, 8, 10, 12, 14, …